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<div class="title">xdphy_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga5ea81bbe1dbd06359901050c0840bceb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga5ea81bbe1dbd06359901050c0840bceb">XDPHY_HW_H_</a></td></tr>
<tr class="memdesc:ga5ea81bbe1dbd06359901050c0840bceb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__xdphy__v1__0.html#ga5ea81bbe1dbd06359901050c0840bceb">More...</a><br /></td></tr>
<tr class="separator:ga5ea81bbe1dbd06359901050c0840bceb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device registers</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register sets of MIPI DPHY </p>
</div></td></tr>
<tr class="memitem:gae4e31f2e733bf381fd409fb8440f0692"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gae4e31f2e733bf381fd409fb8440f0692">XDPHY_CTRL_REG_OFFSET</a>&#160;&#160;&#160;0x00000000</td></tr>
<tr class="memdesc:gae4e31f2e733bf381fd409fb8440f0692"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register.  <a href="group__xdphy__v1__0.html#gae4e31f2e733bf381fd409fb8440f0692">More...</a><br /></td></tr>
<tr class="separator:gae4e31f2e733bf381fd409fb8440f0692"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga84f9c23d5261fbe306b81a330253d013"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga84f9c23d5261fbe306b81a330253d013">XDPHY_HSEXIT_IDELAY_REG_OFFSET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga84f9c23d5261fbe306b81a330253d013"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_EXIT for Tx and Delay for Rx Register.  <a href="group__xdphy__v1__0.html#ga84f9c23d5261fbe306b81a330253d013">More...</a><br /></td></tr>
<tr class="separator:ga84f9c23d5261fbe306b81a330253d013"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab6765e9a336e4a9d4598a2ade003fa3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gab6765e9a336e4a9d4598a2ade003fa3f">XDPHY_INIT_REG_OFFSET</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gab6765e9a336e4a9d4598a2ade003fa3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization Timer Register.  <a href="group__xdphy__v1__0.html#gab6765e9a336e4a9d4598a2ade003fa3f">More...</a><br /></td></tr>
<tr class="separator:gab6765e9a336e4a9d4598a2ade003fa3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadd318931e0e4e7edb5b388566d03d2be"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gadd318931e0e4e7edb5b388566d03d2be">XDPHY_WAKEUP_REG_OFFSET</a>&#160;&#160;&#160;0x0000000C</td></tr>
<tr class="memdesc:gadd318931e0e4e7edb5b388566d03d2be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wakeup Timer for ULPS exit Register.  <a href="group__xdphy__v1__0.html#gadd318931e0e4e7edb5b388566d03d2be">More...</a><br /></td></tr>
<tr class="separator:gadd318931e0e4e7edb5b388566d03d2be"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3bfe3e75d075f2eff4f7d80bc96e117b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga3bfe3e75d075f2eff4f7d80bc96e117b">XDPHY_HSTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga3bfe3e75d075f2eff4f7d80bc96e117b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Watchdog timeout in HS mode Register.  <a href="group__xdphy__v1__0.html#ga3bfe3e75d075f2eff4f7d80bc96e117b">More...</a><br /></td></tr>
<tr class="separator:ga3bfe3e75d075f2eff4f7d80bc96e117b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8434e556500223be8da85f4682ffdb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gaf8434e556500223be8da85f4682ffdb9">XDPHY_ESCTIMEOUT_REG_OFFSET</a>&#160;&#160;&#160;0x00000014</td></tr>
<tr class="memdesc:gaf8434e556500223be8da85f4682ffdb9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Goto Stop state on timeout timer Register.  <a href="group__xdphy__v1__0.html#gaf8434e556500223be8da85f4682ffdb9">More...</a><br /></td></tr>
<tr class="separator:gaf8434e556500223be8da85f4682ffdb9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga06c1da75b71989cce8e56af324969d0a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga06c1da75b71989cce8e56af324969d0a">XDPHY_CLSTATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:ga06c1da75b71989cce8e56af324969d0a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clk lane PHY error Status Register.  <a href="group__xdphy__v1__0.html#ga06c1da75b71989cce8e56af324969d0a">More...</a><br /></td></tr>
<tr class="separator:ga06c1da75b71989cce8e56af324969d0a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0910333b8c2727d176c2e0246a33fdeb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga0910333b8c2727d176c2e0246a33fdeb">XDPHY_DL0STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x0000001C</td></tr>
<tr class="memdesc:ga0910333b8c2727d176c2e0246a33fdeb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 0 PHY error Status Register.  <a href="group__xdphy__v1__0.html#ga0910333b8c2727d176c2e0246a33fdeb">More...</a><br /></td></tr>
<tr class="separator:ga0910333b8c2727d176c2e0246a33fdeb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6bb71b3acc1149468ae0d63a28c37702"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga6bb71b3acc1149468ae0d63a28c37702">XDPHY_DL1STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga6bb71b3acc1149468ae0d63a28c37702"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 1 PHY error Status Register.  <a href="group__xdphy__v1__0.html#ga6bb71b3acc1149468ae0d63a28c37702">More...</a><br /></td></tr>
<tr class="separator:ga6bb71b3acc1149468ae0d63a28c37702"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga86a14e2060bf5c00383ba8e36aa00723"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga86a14e2060bf5c00383ba8e36aa00723">XDPHY_DL2STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000024</td></tr>
<tr class="memdesc:ga86a14e2060bf5c00383ba8e36aa00723"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 2 PHY error Status Register.  <a href="group__xdphy__v1__0.html#ga86a14e2060bf5c00383ba8e36aa00723">More...</a><br /></td></tr>
<tr class="separator:ga86a14e2060bf5c00383ba8e36aa00723"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9ecccc042a9a7f589b7bd9535470e8d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga9ecccc042a9a7f589b7bd9535470e8d9">XDPHY_DL3STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x00000028</td></tr>
<tr class="memdesc:ga9ecccc042a9a7f589b7bd9535470e8d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data lane 3 PHY error Status Register.  <a href="group__xdphy__v1__0.html#ga9ecccc042a9a7f589b7bd9535470e8d9">More...</a><br /></td></tr>
<tr class="separator:ga9ecccc042a9a7f589b7bd9535470e8d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1bd5c4c0e969ac836007ee94e4cfe594"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga1bd5c4c0e969ac836007ee94e4cfe594">XDPHY_HSSETTLE_REG_OFFSET</a>&#160;&#160;&#160;0x00000030</td></tr>
<tr class="memdesc:ga1bd5c4c0e969ac836007ee94e4cfe594"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS Settle Register.  <a href="group__xdphy__v1__0.html#ga1bd5c4c0e969ac836007ee94e4cfe594">More...</a><br /></td></tr>
<tr class="separator:ga1bd5c4c0e969ac836007ee94e4cfe594"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDPHY_CTRL_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for the enabling/disabling and resetting the DPHY </p>
</div></td></tr>
<tr class="memitem:ga0fed5f106749e7c30ccf47874b18d587"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga0fed5f106749e7c30ccf47874b18d587">XDPHY_CTRL_REG_SOFTRESET_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga0fed5f106749e7c30ccf47874b18d587"><td class="mdescLeft">&#160;</td><td class="mdescRight">Soft Reset.  <a href="group__xdphy__v1__0.html#ga0fed5f106749e7c30ccf47874b18d587">More...</a><br /></td></tr>
<tr class="separator:ga0fed5f106749e7c30ccf47874b18d587"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5c2e36eac57592773bcbfcd00155b3a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gad5c2e36eac57592773bcbfcd00155b3a">XDPHY_CTRL_REG_DPHYEN_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gad5c2e36eac57592773bcbfcd00155b3a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable/Disable controller.  <a href="group__xdphy__v1__0.html#gad5c2e36eac57592773bcbfcd00155b3a">More...</a><br /></td></tr>
<tr class="separator:gad5c2e36eac57592773bcbfcd00155b3a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaec36380e3c3cb04055769088e52aebce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gaec36380e3c3cb04055769088e52aebce">XDPHY_CTRL_REG_SOFTRESET_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaec36380e3c3cb04055769088e52aebce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Soft Reset.  <a href="group__xdphy__v1__0.html#gaec36380e3c3cb04055769088e52aebce">More...</a><br /></td></tr>
<tr class="separator:gaec36380e3c3cb04055769088e52aebce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab7278f1be96272bf247b93afbfe5a471"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gab7278f1be96272bf247b93afbfe5a471">XDPHY_CTRL_REG_DPHYEN_OFFSET</a>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:gab7278f1be96272bf247b93afbfe5a471"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for DPHY Enable.  <a href="group__xdphy__v1__0.html#gab7278f1be96272bf247b93afbfe5a471">More...</a><br /></td></tr>
<tr class="separator:gab7278f1be96272bf247b93afbfe5a471"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDPHY_HSEXIT_IDELAY_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register in TX mode acts like HS_EXIT and RX mode acts like IDELAY.</p>
<p>In IDELAY mode, it is used to calibrate input delay </p>
</div></td></tr>
<tr class="memitem:ga88c187e4620de483c6429142188d877f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga88c187e4620de483c6429142188d877f">XDPHY_HSEXIT_IDELAY_REG_READY_MASK</a>&#160;&#160;&#160;0x00000200</td></tr>
<tr class="memdesc:ga88c187e4620de483c6429142188d877f"><td class="mdescLeft">&#160;</td><td class="mdescRight">DLY_RDY of BITSLICE_CONTROL.  <a href="group__xdphy__v1__0.html#ga88c187e4620de483c6429142188d877f">More...</a><br /></td></tr>
<tr class="separator:ga88c187e4620de483c6429142188d877f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga70e60705745389c874fc4931105a958b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga70e60705745389c874fc4931105a958b">XDPHY_HSEXIT_IDELAY_REG_TAP_MASK</a>&#160;&#160;&#160;0x000001FF</td></tr>
<tr class="memdesc:ga70e60705745389c874fc4931105a958b"><td class="mdescLeft">&#160;</td><td class="mdescRight">used in RX data lanes to compensate clock routing delay  <a href="group__xdphy__v1__0.html#ga70e60705745389c874fc4931105a958b">More...</a><br /></td></tr>
<tr class="separator:ga70e60705745389c874fc4931105a958b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga66536940ca2123d330e9e753116baa76"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga66536940ca2123d330e9e753116baa76">XDPHY_HSEXIT_IDELAY_REG_READY_OFFSET</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:ga66536940ca2123d330e9e753116baa76"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for READY bit.  <a href="group__xdphy__v1__0.html#ga66536940ca2123d330e9e753116baa76">More...</a><br /></td></tr>
<tr class="separator:ga66536940ca2123d330e9e753116baa76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a16c8bbc59f02759ff527a41cc15441"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga4a16c8bbc59f02759ff527a41cc15441">XDPHY_HSEXIT_IDELAY_REG_TAP_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga4a16c8bbc59f02759ff527a41cc15441"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for TAP.  <a href="group__xdphy__v1__0.html#ga4a16c8bbc59f02759ff527a41cc15441">More...</a><br /></td></tr>
<tr class="separator:ga4a16c8bbc59f02759ff527a41cc15441"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDPHY_INIT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used for lane Initialization.</p>
<p>Recommended to use 1ms or longer in for TX mode and 200us-500us for RX mode </p>
</div></td></tr>
<tr class="memitem:ga58bacf2c4977744f53b942c5e66b2ac7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga58bacf2c4977744f53b942c5e66b2ac7">XDPHY_INIT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga58bacf2c4977744f53b942c5e66b2ac7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Init Timer value in ns.  <a href="group__xdphy__v1__0.html#ga58bacf2c4977744f53b942c5e66b2ac7">More...</a><br /></td></tr>
<tr class="separator:ga58bacf2c4977744f53b942c5e66b2ac7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94cc74bdeabfb39fb3491ca3d9f69505"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga94cc74bdeabfb39fb3491ca3d9f69505">XDPHY_INIT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga94cc74bdeabfb39fb3491ca3d9f69505"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Init Timer.  <a href="group__xdphy__v1__0.html#ga94cc74bdeabfb39fb3491ca3d9f69505">More...</a><br /></td></tr>
<tr class="separator:ga94cc74bdeabfb39fb3491ca3d9f69505"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XDPHY_WAKEUP_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Wakeup time delay for ULPS exit. </p>
</div></td></tr>
<tr class="memitem:gae02301b9b34a5cdaecabaef744dd8eb4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gae02301b9b34a5cdaecabaef744dd8eb4">XDPHY_WAKEUP_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:gae02301b9b34a5cdaecabaef744dd8eb4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Wakeup timer value.  <a href="group__xdphy__v1__0.html#gae02301b9b34a5cdaecabaef744dd8eb4">More...</a><br /></td></tr>
<tr class="separator:gae02301b9b34a5cdaecabaef744dd8eb4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga99fd9e57dfbc1124d0d6e34e18244984"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga99fd9e57dfbc1124d0d6e34e18244984">XDPHY_WAKEUP_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga99fd9e57dfbc1124d0d6e34e18244984"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Wakeup value.  <a href="group__xdphy__v1__0.html#ga99fd9e57dfbc1124d0d6e34e18244984">More...</a><br /></td></tr>
<tr class="separator:ga99fd9e57dfbc1124d0d6e34e18244984"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XDPHY_HSTIMEOUT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program watchdog timer in high speed mode.</p>
<p>Default value is 65541. Valid range 1000-65541. </p>
</div></td></tr>
<tr class="memitem:ga74cdf673408c25d6cc6386b300fd51c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga74cdf673408c25d6cc6386b300fd51c9">XDPHY_HSTIMEOUT_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga74cdf673408c25d6cc6386b300fd51c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_T/RX_TIMEOUT Received.  <a href="group__xdphy__v1__0.html#ga74cdf673408c25d6cc6386b300fd51c9">More...</a><br /></td></tr>
<tr class="separator:ga74cdf673408c25d6cc6386b300fd51c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d56bcabd214547834ab29d9c3e11c31"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga7d56bcabd214547834ab29d9c3e11c31">XDPHY_HSTIMEOUT_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga7d56bcabd214547834ab29d9c3e11c31"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Timeout.  <a href="group__xdphy__v1__0.html#ga7d56bcabd214547834ab29d9c3e11c31">More...</a><br /></td></tr>
<tr class="separator:ga7d56bcabd214547834ab29d9c3e11c31"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XDPHY_ESCTIMEOUT_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains Rx Data Lanes timeout for watchdog timer in escape mode. </p>
</div></td></tr>
<tr class="memitem:ga5436842b8eb844edfd6f732f04d82983"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga5436842b8eb844edfd6f732f04d82983">XDPHY_ESCTIMEOUT_REG_VAL_MASK</a>&#160;&#160;&#160;0xFFFFFFFF</td></tr>
<tr class="memdesc:ga5436842b8eb844edfd6f732f04d82983"><td class="mdescLeft">&#160;</td><td class="mdescRight">Escape Timout Value.  <a href="group__xdphy__v1__0.html#ga5436842b8eb844edfd6f732f04d82983">More...</a><br /></td></tr>
<tr class="separator:ga5436842b8eb844edfd6f732f04d82983"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96f1dbf150464ae3569a7ec188806c09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga96f1dbf150464ae3569a7ec188806c09">XDPHY_ESCTIMEOUT_REG_VAL_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:ga96f1dbf150464ae3569a7ec188806c09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Timeout.  <a href="group__xdphy__v1__0.html#ga96f1dbf150464ae3569a7ec188806c09">More...</a><br /></td></tr>
<tr class="separator:ga96f1dbf150464ae3569a7ec188806c09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XDPHY_CLSTATUS_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the clock lane status and state machine control. </p>
</div></td></tr>
<tr class="memitem:gaae3b5a38d6148049808a4d7f93eef6fd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gaae3b5a38d6148049808a4d7f93eef6fd">XDPHY_CLSTATUS_REG_ERRCTRL_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gaae3b5a38d6148049808a4d7f93eef6fd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane control error.  <a href="group__xdphy__v1__0.html#gaae3b5a38d6148049808a4d7f93eef6fd">More...</a><br /></td></tr>
<tr class="separator:gaae3b5a38d6148049808a4d7f93eef6fd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21324d38abce3de384dd8c0fa3efd3cd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga21324d38abce3de384dd8c0fa3efd3cd">XDPHY_CLSTATUS_REG_STOPSTATE_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga21324d38abce3de384dd8c0fa3efd3cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clock lane stop state.  <a href="group__xdphy__v1__0.html#ga21324d38abce3de384dd8c0fa3efd3cd">More...</a><br /></td></tr>
<tr class="separator:ga21324d38abce3de384dd8c0fa3efd3cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5be1da7f80bac419a10f6ce5d052b6c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga5be1da7f80bac419a10f6ce5d052b6c1">XDPHY_CLSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga5be1da7f80bac419a10f6ce5d052b6c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialization done bit.  <a href="group__xdphy__v1__0.html#ga5be1da7f80bac419a10f6ce5d052b6c1">More...</a><br /></td></tr>
<tr class="separator:ga5be1da7f80bac419a10f6ce5d052b6c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1541970411eabf3d25f12902d2602abe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga1541970411eabf3d25f12902d2602abe">XDPHY_CLSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga1541970411eabf3d25f12902d2602abe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set in ULPS mode.  <a href="group__xdphy__v1__0.html#ga1541970411eabf3d25f12902d2602abe">More...</a><br /></td></tr>
<tr class="separator:ga1541970411eabf3d25f12902d2602abe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaabcdc97a4b6fe84878848175e059319a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gaabcdc97a4b6fe84878848175e059319a">XDPHY_CLSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gaabcdc97a4b6fe84878848175e059319a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Low, High, Esc mode.  <a href="group__xdphy__v1__0.html#gaabcdc97a4b6fe84878848175e059319a">More...</a><br /></td></tr>
<tr class="separator:gaabcdc97a4b6fe84878848175e059319a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0d8a99b274aecc21c3123cf57107ea0"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPHY_CLSTATUS_ALLMASK</b></td></tr>
<tr class="separator:gad0d8a99b274aecc21c3123cf57107ea0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa857f48d553b9ed179970cdfbf80c742"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gaa857f48d553b9ed179970cdfbf80c742">XDPHY_CLSTATUS_REG_ERRCTRL_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:gaa857f48d553b9ed179970cdfbf80c742"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Control Error on Clock.  <a href="group__xdphy__v1__0.html#gaa857f48d553b9ed179970cdfbf80c742">More...</a><br /></td></tr>
<tr class="separator:gaa857f48d553b9ed179970cdfbf80c742"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga72c5fdb7a5278e673f244b55e1131ea0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga72c5fdb7a5278e673f244b55e1131ea0">XDPHY_CLSTATUS_REG_STOPSTATE_OFFSET</a>&#160;&#160;&#160;4</td></tr>
<tr class="memdesc:ga72c5fdb7a5278e673f244b55e1131ea0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State on Clock.  <a href="group__xdphy__v1__0.html#ga72c5fdb7a5278e673f244b55e1131ea0">More...</a><br /></td></tr>
<tr class="separator:ga72c5fdb7a5278e673f244b55e1131ea0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4ede74f9800a80cf16a164e286892a2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gac4ede74f9800a80cf16a164e286892a2">XDPHY_CLSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gac4ede74f9800a80cf16a164e286892a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization Done.  <a href="group__xdphy__v1__0.html#gac4ede74f9800a80cf16a164e286892a2">More...</a><br /></td></tr>
<tr class="separator:gac4ede74f9800a80cf16a164e286892a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga96a03a5d83c97392523b37f5a652ba99"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga96a03a5d83c97392523b37f5a652ba99">XDPHY_CLSTATUS_REG_ULPS_OFFSET</a>&#160;&#160;&#160;2</td></tr>
<tr class="memdesc:ga96a03a5d83c97392523b37f5a652ba99"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for ULPS.  <a href="group__xdphy__v1__0.html#ga96a03a5d83c97392523b37f5a652ba99">More...</a><br /></td></tr>
<tr class="separator:ga96a03a5d83c97392523b37f5a652ba99"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafe0395442a9bccc4990fa50bb2aee9dc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gafe0395442a9bccc4990fa50bb2aee9dc">XDPHY_CLSTATUS_REG_MODE_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gafe0395442a9bccc4990fa50bb2aee9dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Mode bits.  <a href="group__xdphy__v1__0.html#gafe0395442a9bccc4990fa50bb2aee9dc">More...</a><br /></td></tr>
<tr class="separator:gafe0395442a9bccc4990fa50bb2aee9dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Bitmasks and offsets of XDPHY_DLxSTATUS_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register contains the data lanes status </p>
</div></td></tr>
<tr class="memitem:ga5e883a6b8e54d4a9399a9f66a2b69087"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga5e883a6b8e54d4a9399a9f66a2b69087">XDPHY_DLXSTATUS_REG_PACKETCOUNT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga5e883a6b8e54d4a9399a9f66a2b69087"><td class="mdescLeft">&#160;</td><td class="mdescRight">Packet Count.  <a href="group__xdphy__v1__0.html#ga5e883a6b8e54d4a9399a9f66a2b69087">More...</a><br /></td></tr>
<tr class="separator:ga5e883a6b8e54d4a9399a9f66a2b69087"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad64284d735349ca7df0d3ef2d218cc1e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gad64284d735349ca7df0d3ef2d218cc1e">XDPHY_DLXSTATUS_REG_STOP_MASK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gad64284d735349ca7df0d3ef2d218cc1e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stop State on data lane.  <a href="group__xdphy__v1__0.html#gad64284d735349ca7df0d3ef2d218cc1e">More...</a><br /></td></tr>
<tr class="separator:gad64284d735349ca7df0d3ef2d218cc1e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga115ba74c0024df0afb08ac195b2516db"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga115ba74c0024df0afb08ac195b2516db">XDPHY_DLXSTATUS_REG_ESCABRT_MASK</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:ga115ba74c0024df0afb08ac195b2516db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane Esc timeout occurs.  <a href="group__xdphy__v1__0.html#ga115ba74c0024df0afb08ac195b2516db">More...</a><br /></td></tr>
<tr class="separator:ga115ba74c0024df0afb08ac195b2516db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6d0dfe6cdce39bb092251a352bbdd2c1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga6d0dfe6cdce39bb092251a352bbdd2c1">XDPHY_DLXSTATUS_REG_HSABRT_MASK</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga6d0dfe6cdce39bb092251a352bbdd2c1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set on Data Lane HS timeout.  <a href="group__xdphy__v1__0.html#ga6d0dfe6cdce39bb092251a352bbdd2c1">More...</a><br /></td></tr>
<tr class="separator:ga6d0dfe6cdce39bb092251a352bbdd2c1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3b28f74a1333b48eedf55e43df7c22cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga3b28f74a1333b48eedf55e43df7c22cb">XDPHY_DLXSTATUS_REG_INITDONE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga3b28f74a1333b48eedf55e43df7c22cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set after initialization.  <a href="group__xdphy__v1__0.html#ga3b28f74a1333b48eedf55e43df7c22cb">More...</a><br /></td></tr>
<tr class="separator:ga3b28f74a1333b48eedf55e43df7c22cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga17aba55613d160e07e0e9540923696b8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga17aba55613d160e07e0e9540923696b8">XDPHY_DLXSTATUS_REG_ULPS_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga17aba55613d160e07e0e9540923696b8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set when DPHY in ULPS mode.  <a href="group__xdphy__v1__0.html#ga17aba55613d160e07e0e9540923696b8">More...</a><br /></td></tr>
<tr class="separator:ga17aba55613d160e07e0e9540923696b8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacb7931a2a11c01f1a0bf86eaf3813ad1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gacb7931a2a11c01f1a0bf86eaf3813ad1">XDPHY_DLXSTATUS_REG_MODE_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gacb7931a2a11c01f1a0bf86eaf3813ad1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Mode (Esc, Low, High) of Data Lane.  <a href="group__xdphy__v1__0.html#gacb7931a2a11c01f1a0bf86eaf3813ad1">More...</a><br /></td></tr>
<tr class="separator:gacb7931a2a11c01f1a0bf86eaf3813ad1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ce7be3cdf98b126f61f647f1dfdbe5c"><td class="memItemLeft" align="right" valign="top">
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XDPHY_DLXSTATUS_ALLMASK</b></td></tr>
<tr class="separator:ga0ce7be3cdf98b126f61f647f1dfdbe5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad0aef49004b2cf549d98ad9f596db44c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gad0aef49004b2cf549d98ad9f596db44c">XDPHY_DLXSTATUS_REG_PACKCOUNT_OFFSET</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:gad0aef49004b2cf549d98ad9f596db44c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset packet count.  <a href="group__xdphy__v1__0.html#gad0aef49004b2cf549d98ad9f596db44c">More...</a><br /></td></tr>
<tr class="separator:gad0aef49004b2cf549d98ad9f596db44c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga47eb15589bbe8d3cec12bdff19d1ceea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga47eb15589bbe8d3cec12bdff19d1ceea">XDPHY_DLXSTATUS_REG_STOP_OFFSET</a>&#160;&#160;&#160;6</td></tr>
<tr class="memdesc:ga47eb15589bbe8d3cec12bdff19d1ceea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Stop State.  <a href="group__xdphy__v1__0.html#ga47eb15589bbe8d3cec12bdff19d1ceea">More...</a><br /></td></tr>
<tr class="separator:ga47eb15589bbe8d3cec12bdff19d1ceea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae43b92b04c91408a2d996cb3c160c451"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gae43b92b04c91408a2d996cb3c160c451">XDPHY_DLXSTATUS_REG_ESCABRT_OFFSET</a>&#160;&#160;&#160;5</td></tr>
<tr class="memdesc:gae43b92b04c91408a2d996cb3c160c451"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Escape Abort.  <a href="group__xdphy__v1__0.html#gae43b92b04c91408a2d996cb3c160c451">More...</a><br /></td></tr>
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<tr class="memitem:ga257086d0079a73f81869b91065044dc9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga257086d0079a73f81869b91065044dc9">XDPHY_DLXSTATUS_REG_HSABRT_OFFSET</a>&#160;&#160;&#160;4</td></tr>
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<tr class="memitem:gaa0966d879c4b079fe1fb3512248710e7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gaa0966d879c4b079fe1fb3512248710e7">XDPHY_DLXSTATUS_REG_INITDONE_OFFSET</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:gaa0966d879c4b079fe1fb3512248710e7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for Initialization done.  <a href="group__xdphy__v1__0.html#gaa0966d879c4b079fe1fb3512248710e7">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Bitmask and offset of XDPHY_HSSETTLE_REG_OFFSET register</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>This register is used to program the HS SETTLE register.</p>
<p>Default value is 135 + 10UI. </p>
</div></td></tr>
<tr class="memitem:ga81d0494a47fc8373620ff052cc42ea80"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#ga81d0494a47fc8373620ff052cc42ea80">XDPHY_HSSETTLE_REG_TIMEOUT_MASK</a>&#160;&#160;&#160;0x1FF</td></tr>
<tr class="memdesc:ga81d0494a47fc8373620ff052cc42ea80"><td class="mdescLeft">&#160;</td><td class="mdescRight">HS_SETTLE value.  <a href="group__xdphy__v1__0.html#ga81d0494a47fc8373620ff052cc42ea80">More...</a><br /></td></tr>
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<tr class="memitem:gad87dd909a0ccacacd26c2622f86db919"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__xdphy__v1__0.html#gad87dd909a0ccacacd26c2622f86db919">XDPHY_HSSETTLE_REG_TIMEOUT_OFFSET</a>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gad87dd909a0ccacacd26c2622f86db919"><td class="mdescLeft">&#160;</td><td class="mdescRight">Bit offset for HS_SETTLE.  <a href="group__xdphy__v1__0.html#gad87dd909a0ccacacd26c2622f86db919">More...</a><br /></td></tr>
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